Ivo J. ter Horst - Performance Evaluation in an Early Development Phase

author:Ivo J. ter Horst
title:Performance Evaluation in an Early Development Phase
keywords:performance evaluation, UML
committee:dr. D.N. Jansen (1st supervisor)
dr. M.I.A. Stoelinga
drs. A.G. Kleppe
ir. M.H.J. Glandrup (Thales)
dr.ir. Rene C. Scholten (Thales)
graduation date:February 2007 (mark: 8/10)


In the area of performance evaluation, a lot of research has been done on real-time constraints such as communication latencies and throughput requirements. However, almost no research has been conducted on performance evaluation in a very early development phase. The study presented in this thesis provides a method that can be applied to do performance evaluation in an early development phase, even when the structure of software and hardware are just being defined.

Performance evaluation of combat management systems at Thales Naval Nederland is currently performed too late in the development process. Failure to meet performance goals can be costly and should be avoided, so early discovery of problems is important. Instead of the calculations in large Excel sheets which were used, this thesis presents a UML model with which the structure and performance information of a system can clearly be defined. To support an engineer in defining the structure of software and hardware, the well-known modeling language UML is used. To specify the systems developed by Thales, we have created number of stereotypes and grouped them in the new UML profile TProfile. The stereotypes define default elements an engineer can use to define the structure of software and hardware in a hierarchical way. Allocation relationships link software to hardware and define which parts of the software run on which hardware parts.

Performance information can be added to all elements of the structural model of a system in terms of budgets. A budget defines an amount of resources provided by the hardware or required by the software system. We have defined a small expression-based language to express budget values, which are either fixed, or can depend on other budgets. We thus provide the possibility to express dependencies between dif ferent parts of the system. Constraints are defined on allocation relationships, where the software meets the hardware. A constraint relates the budget of a software element to the budget of a hardware element and defines a restriction on that relationship. This allows engineers to express whether the software system fits on the hardware system.

As the UML models of systems tend to grow large and a lot of budgets and constraints are added, evaluation of the constraints becomes a hard task. Automatic constraint verification is therefore provided by our System Verifier Tool, which integrates with Rational Software Architect (RSA), the tool used within Thales to create UML models. We use RSA’s UML modeling functionality of RSA and introduce the TProfile with our System Verifier Tool, which recognizes the elements relevant to Thales by means of the stereotypes. Because of the integration of the System Verifier Tool in RSA, verification of all constraints created for a system can be done at the push of a button. Verification results are presented clearly to the engineer.

The System Verifier Tool allows engineers to easily experiment with the structure of hardware and software, budget values and constraints and thus supports system development in an early phase.